1. Field of the Invention
The present invention relates to a method of making metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to a method of making metal oxide semiconductors field effect transistors with a lightly doped drain (LDD) structure having a recess type gate.
2. Description of the Prior Art
Referring to FIGS. 1a and 1b, there is shown a general construction of a prior art metal oxide semiconductor field effect transistor (MOSFET).
As shown in FIG. 1a, the MOSFET comprises a substrate 1 of a predetermined conduction type, a gate oxide layer 2 coated on the substrate 1 and a gate 3 coated on the oxide layer 2. The MOSFET also comprises a drain region 4 and a source region 5 formed on the substrate below opposite edge portions of the gate 2, respectively.
The operation of the MOSFET with the abovementioned construction will now be described in conjunction with FIGS. 1a and 1b.
As a drive voltage is applied to the gate 3, a charging occurs between holes of the gate 3 and electrons of the silicon substrate 1, across the gate oxide layer 2, thereby forming a channel having a predetermined thickness between the drain region 4 and the source region 5. Electrons flow from the source region 5 to the drain region 4. At this time, a peak electric field is formed at the edge portion of the gate 3, where the gate 3 and the drain region 4 are in contact with each other.
That is, the carrier concentration, shown as a solid line in FIG. 1b, is sharply decreased in the area where the gate 3 and the drain region 4 are in contact with each other, while it recovers in the drain region 4 which is of a high concentration n-type, as shown in FIG. 1b. As a result, the gate oxide layer 2, which functions to isolate electrically the gate 3 and the drain region 4, may be damaged by hot electrons generated at the edge portion of the gate 3. The hot electrons are then trapped in the gate 3, via the gate oxide layer 2. The trapped electrons are re-combined with holes of the gate 3. This phenomenon is referred to as a "Hot Carrier Effect". Due to the hot carrier effect, the transistor actually requires a gate bias voltage higher than a predetermined voltage for driving it.
Various techniques for reducing the hot carrier effect have been proposed. Referring to FIGS. 1c and 1d, there is illustrated an example of these techniques.
As shown in FIG. 1c, the exemplified MOSFET construction comprises a low doping concentration n-type drain region 6 formed between the gate 3 and the high doping concentration n-type drain region 4 and adapted to degrade current at the edge portion of the gate 3.
As the carrier concentration decreases, the depletion region in the channel increases, thereby causing the total channel length d to be lengthened. The above construction utilizes the effect of a lengthened total channel length.
Accordingly, the intensity E of the electric field in this case is decreased to reduce the hot carrier effect, according to the following formula: EQU E=V / d ... (1)
In this case, however, the length of the low concentration n-type drain region 6 should be sufficiently long. This is because the intensity E of the electric field becomes low only when the drain bias effects on the area are as large as possible, via the high concentration n-type drain region 4.
Therefore, as the intensity E of the electric field decreases, the depletion region in the channel extends from the low concentration n-type drain region 6 to a low concentration source region 7, so as to be enlarged, thereby reducing the hot carrier effect.
Also, the low concentration n-type drain region 6 should be overlapped with the gate 3. If the gate does not overlap the drain region 6, as shown in FIGS. 1c and 1d, the carrier concentration decreases abruptly at the portion D of the low concentration n-type drain region 6 which is withdrawn from the voltage control of the gate 3. As a result, the intensity of the electric field increases at the portion D of the low concentration n-type drain region 6. That is, the doping concentration of the transistor increases gradually in the order of the p-type substrate 1, the low concentration n-type drain 6, and the high concentration n-type drain 4, as shown by the dotted line in FIG. 1d. As a predetermined voltage is applied to the gate 3, the carrier concentration is maintained at a predetermined level at the p-type substrate and increases gradually at the low concentration n-type drain 6, as shown by the solid line in FIG. 1d. At the position where the voltage control of the gate 3 ends, the carrier concentration decreases abruptly and then recovers at the high concentration n-type drain 4. As a result, the intensity of the electric field is increased at the region where the carrier concentration decreases, thereby causing the hot carrier effect.
FIGS. 2a to 2c illustrate a method of making a MOSFET comprising a gate completely overlapping the low concentration n-type drain and source region. This method is disclosed in a paper, "A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS)" published in IEEE Electron Device Letters Vol. 11 No. 5., pages 221-222, published in May, 1990.
As shown in FIG. 2a, a thin initial oxide layer 12 is grown on a silicon substrate 11. On the initial oxide layer 12, a first thin polysilicon layer 13 and thin oxide layer 14 and formed, in turn. On the oxide layer 14, a second polysilicon layer 15 is formed, which has the thickness thicker than that of the first polysilicon layer 13.
Thereafter, the second polysilicon layer 15 is subjected to a photo lithography process to define a gate therein, as shown in FIG. 2b. The second polysilicon layer 15 is then etched back to remove the unnecessary portion therefrom. Subsequently, low concentration n-type ions are injected into the substrate 11, via the first polysilicon layer 13 and the initial oxide layer 12, to form a low concentration n-type drain 16 and a low concentration n-type source 19. The second oxide layer 14 is then subjected to a wet etch utilizing a neutralized dilute HF solution.
Thereafter, a third polysilicon layer 15a is coated on the overall exposed surface, as shown in FIG. 2c. The second and the third polysilicon layer 15 and 15A, and the initial oxide layer 12 are then etched back, in the same manner as the first layer 13, thereby forming the gate surrounded by a side wall.
Subsequently, high concentration n-type ions are injected into the substrate 11, forming a high concentration n-type source 20 and a high concentration n-type drain 18.
The portion of silicon substrate 11 between the low concentration n-type drain 16 and the low concentration n-type source 19 is subjected to an ion injection, to provide a stop to a punchthrough effect.
In the above-mentioned construction, however, the channel formed between the low concentration n-type drain 16 and the low concentration n-type source 19 has the length of submicron or deep-submicron dimension, so that the reduction of the hot carrier effect is limited. In the construction, there is also a disadvantage of the increase in the junction capacitance between the gate and the source and between the gate and the drain. Also, the doping compensation effect caused by the injection of low concentration n-type ions can not be reduced due to the injection of ions into the channel.